1. Field of the Invention
The present invention relates to a protection device, particularly to a soft error protection device.
2. Description of the Related Art
Soft error is a transient fault, induced by one particle in cosmic striking the sensitive region of a transistor with deposited charges, latched by a memory element after propagation. In recent years, since the technology keeps scaling down and the parasitic capacitance in the circuit becomes smaller, the circuit is more susceptible to the soft error. Therefore, many advance architectures of the latch were proposed to protect the occurrence of soft error.
The U.S. Pat. No. 6,380,781 used the loading transistor to enlarge the capacitance and eliminate the unexpected pulse. However, the loading transistor may cause an unequal transient and affect the normal operation. Therefore, the U.S. Pat. No. 6,573,774 disclosed two duplications of latches were proposed to vote and select the certain logic value, but such design has area overhead due to the replicated latches. Moreover, C-element was proposed in the U.S. Pat. No. 7,038,515 to protect the soft error and corrects the error value. However, these three techniques can only prevent the soft error in the memory cell but cannot protect the occurrence of soft error in the combination logics. As a result, Build-In Soft Error Resilience (BISER) was proposed in the conventional technology to protect the soft error occurring on both memory and combinational circuit. BISER uses the double latching, delay buffer and C-element to achieve the soft-error protection. However, BISER still has some issues and can be improved. For example, it requires a certain number of transistors, which also increases the probability of soft error and results in more area overhead.
To overcome the abovementioned problems, the present invention provides a soft error protection device, so as to solve the afore-mentioned problems of the prior art.